Nitride semiconductor materials such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), indium aluminum gallium nitride (InAlGaN) and the like involve advantageous features such as higher dielectric breakdown voltage, higher thermal conductivity, higher electronic saturation velocity and the like. Due to these advantageous features, the nitride semiconductor materials are promising semiconductor materials for the use in manufacturing electric power devices in the field of radio frequency (RF) devices or manufacturing high power devices, and thus, in recent years, developments for achieving practical realizations of the field effect transistors employing nitride semiconductor material are actively conducted.
These applications require the enhancement (normally off) type devices, which require no negative DC bias power source to gate electrodes of field effect transistors. FIG. 6 shows an example of a conventionally proposed structure of an enhancement (normally off) type field effect transistor employing a nitride semiconductor material (see Japanese Patent Laid-Open No. 2005-183,733). A configuration of the enhancement type field effect transistor employing a nitride semiconductor illustrated in FIG. 6 will be briefly described. The enhancement type field effect transistor shown in FIG. 6 has a structure of so-called high electron mobility transistor (HEMT). The field effect transistor shown in FIG. 6 includes a substrate 1 having higher resistance such as sapphire substrate and a buffer layer 2 composed of GaN and having a thickness of 50 nm provided on the substrate 1. A channel layer 3 composed of GaN and having a thickness 400 nm, an intermediate layer 9 composed of aluminum nitride (AlN) and having a thickness of 1 nm and an electron-supplying layer 4 composed of undoped Al0.2Ga0.8N and having a thickness of 30 nm are consecutively deposited on the buffer layer 2 to form a hetero junction structure. In addition, a source electrode S, a gate G and a drain electrode D are two-dimensionally arranged.
The field effect transistor having a conventional HEMT structure shown in FIG. 6 is provided with a recessed structure in a section 8 corresponding to the section right under the gate electrode G. More specifically, the thickness of the undoped Al0.2Ga0.8N layer in the section 8 is 5 nm, while other sections of the undoped Al0.2Ga0.8N layer constituting the electron-supplying layer 4 except the section 8 is 30 nm. In other sections thereof except the section 8, electron supplied from the electron-supplying layer 4 composed of the undoped Al0.2Ga0.8N is accumulated in the hetero junction interface between the intermediate layer 9 composed of AlN and the channel layer 3 composed of GaN. Electron accumulated in the hetero junction interface between the intermediate layer 9 composed of AlN and the channel layer 3 composed of GaN constitutes a two-dimensional electron gas 6.
On the other hand, in the section 8, a depleted layer resulted from the presence of the gate electrode G, which is provided in the surface of the undoped Al0.2Ga0.8N layer, reaches the channel layer 3 composed of GaN, even if the bias voltage of the gate electrode G is set to 0 V. As a result, no accumulation of electron is caused in the hetero junction interface between the intermediate layer 9 composed of AlN and the channel layer 3 composed of GaN located right under the section 8. More specifically, no two-dimensional electron gas 6 is formed in the section right under the region of the section 8 in the condition that the bias voltage of the gate electrode G is set to 0 V. Therefore, in the condition that the gate voltage VG applied to the gate electrode G is 0 V, a normally off condition is achieved, in which no drain current ID flows even if a drain voltage VD is applied between the source electrode S and the drain electrode D. On the other hand, when the gate voltage VG applied to the gate electrode G is biased to provide positive voltage of higher than a threshold voltage, drain current ID flows. This allows achieving the enhancement (normally off) type field effect transistor.
Next, the process operations for manufacturing the field effect transistor having the conventional HEMT structure as shown in FIG. 6 will be briefly described in reference to FIG. 7. First of all, the sapphire substrate 1 is introduced in a metal organic chemical vapor deposition (MOCVD) apparatus, and the MOCVD apparatus is evacuated with a turbo pump to achieve a vacuum pressure of not higher than 1×10−6 hPa. Then, the pressure is increased to 100 hPa, and the temperature of the substrate 1 is elevated to 1,100 degrees C. Once the substrate temperature is stabilized, then the substrate 1 is rotated at 900 rpm. A source gas containing trimethylgallium (TMG) at a flow rate of 100 cm3/min. and ammonia at a flow rate of 12 l/min. is introduced over the surface of the substrate 1 to carry out a growth of the buffer layer 2 composed of GaN. The deposition time of 4 min. (240 sec.) provides a thickness of the buffer layer 2 of about 50 nm.
Then, trimethylgallium (TMG) at a flow rate of 100 cm3/min. and ammonia (NH3) at a flow rate of 12 l/min. are introduced over the buffer layer 2 to carry out a growth of the channel layer 3 composed of GaN. The deposition time of 1,000 sec. provides a thickness of the channel layer 3 of 400 nm.
Then, trimethylaluminum (TMA) at a flow rate of 50 cm3/min. and ammonia at a flow rate of 12 Umin. are introduced to carry out a growth of the intermediate layer 9 composed of undoped AlN. Continuously, trimethylaluminum (TMA) at a flow rate of 50 cm3/min., trimethylgallium (TMG) at a flow rate of 100 cm3/min., and ammonia at a flow rate of 12 l/min., are introduced to carry out a growth of the electron-supplying layer 4 composed of Al0.2Ga0.8N. The deposition time of 40 sec. provides a thickness of the electron-supplying layer 4 of 30 nm. The layer structure A0 shown in FIG. 7(a) is completed by the above-described operations.
After the epitaxial growth for the layer structure A0 is completed, a silicon dioxide (SiO2) film 10 is formed over the entire surface of the layer structure A0. An opening is provided in the sectional region of the SiO2 film 10 associated with the section 8 corresponding to the section right under the gate to expose a section of the electron-supplying layer 4 corresponding thereto. Then, the electron-supplying layer 4 having the total thickness of 30 nm is partially oxidized to a depth of 25 nm from the surface at a normal pressure, at a flow rate of oxygen gas of not higher than 5 l/min. and at a temperature of 900 degrees C. to form an oxide layer 11 (see layer structure A1 in FIG. 7(b)).
Such oxidation process provides the thickness of the semiconductor layer of 5 nm in the section 8 of the electron-supplying layer 4 corresponding to the section right under the gate, which means that the thickness of the section 8 is thinner than the thickness of the semiconductor layer constituting the other section of the electron-supplying layer 4 except the section 8 corresponding to the section right under the gate. Subsequently, a phosphoric acid based-, a hydrochloric acid based-, a fluorinated acid based- or a nitric acid based-etchant is employed to consecutively remove the oxide layer 11 and the SiO2 film 10 via a wet etching process. As a result, the concave section 7 is formed in the electron-supplying layer 4.
The two-dimensional electron gas 6 disappears from the section of the channel layer 3 in the concave section 7, as shown in the layer structure A2 of FIG. 7(c), even in the stage that the Schottky conjunction with the surface of electron-supplying layer 4 and the gate electrode G is not yet formed. More specifically, even in the condition that no Schottky conjunction is formed on the surface of the electron-supplying layer 4, the conduction band edge Ec of the section right under the concave section 7 in the channel layer 3 in the interface between the intermediate layer 9 and the channel layer 3 is in higher energy level than Fermi level Ef.
After the completion of the etching process, the source electrode S and the drain electrode D (both composed of Al/Ti/Au with thickness of 100 nm/100 nm/200 nm), and the gate electrode G in the concave section 7 (composed of Pt/Au with thickness of 100 nm/200 nm) are formed via an electron beam (EB) deposition process. As described above, the enhancement (normally off) type field effect transistor employing a nitride semiconductor according to the conventional technology as shown in FIG. 6 is obtained.
In addition to above, similar background technologies include technologies disclosed in Japanese Patent Laid-Open No. 2001-085,670 and Japanese Patent Laid-Open No. 2004-273,655.    [Patent Document 1] Japanese Patent Laid-Open No. 2005-183,733    [Patent Document 2] Japanese Patent Laid-Open No. 2001-085,670    [Patent Document 3] Japanese Patent Laid-Open No. 2004-273,655